For the last past two decades, integrated circuits have been composed of logical and physical units made of gating elements and wiring elements to interconnect the logic. There has been a trend toward larger stand-alone functional units called macros. These macros use a substantial silicon area on a semiconductor chip. One of the newer units is an embedded field programmable gate array (FPGA) macro. These macros use up a large area of a chip and a significant portion of the wiring channels that pass through the chip. This factor creates an inability to wire through the chip in the area of the macro.
Currently, FPGAs are becoming an accepted component embedded within standard chip designs along with semi-custom cores and memory macros. Standard block design is a term that is used to describe NANDS, NORS and other types of individual books that comprise a logic family. The books are designed with standard block implementation with simple books, such as an inverter taking one block and more complex books taking several blocks. Technology has now migrated to less than 100 nm ground rules, or restrictions on how shapes can be laid out to enable a part to be made. Because of this trend, the performance effect due to wiring is becoming the primary factor of timing closure of the input and output signals. Depending upon the functions around the FPGA, the required porosity through the FPGA as initially designed may not match the required FPGA at a later time. These FPGAs are dense macros within the chip that require significant metal usage, often resulting in unacceptable wiring blockage such that key, timing critical wires must be routed around the macro, resulting in unacceptable timing delays. Accordingly, procedures for reducing or eliminating such timing delays are needed.
FPGAs are structures that are made up of collections of uniform slices. Each slice can be programmed for a segment of the total user function. In the previous implementations, FPGAs were often large dedicated chips. The current trend is to integrate these macros onto designs with other logic. As circuit density reaches 90 nm and less, the effective number of logic functions that can be integrated onto the chip is large enough to desire these FPGAs to be distributed throughout the design. Due to the significant usage of metal layers in FPGA circuitry, channels are blocked when the arrays are embedded in the chip. As a result, wires that need to travel from a circuit on one side of the FPGA to the other side within the chip will need to be routed around the FPGA. This can cause unacceptably long signal delays impacting overall chip performance and reliability because of the longer circuit paths. With current construction techniques, the embedded FPG arrays or other cores are fully obstructed on all layers. Because of the high blockage, or low porosity, power buses typically have only one contact with individual devices, resulting in relatively high effective resistance. One solution would be to place uniform wiring channels at regular intervals through an FPGA during the macro's design but, depending upon the usage, there may be either too many wiring channels or not enough. This is an inefficient use of the channels.
In Research Disclosure n337 05-92, dated May 1992, entitled “Adjustable Wiring Porosity in Flexible Gate array Design”, J A Iadanza et al describe the adding of variable wire-through capability to a standard circuit or array design program to provide versatility to optimize use of first and second level wiring in a design. The capability allows minimization of space required for wiring in a wide range of array size and word dimensions. They go on to state that, in conventional engineering design system (EDS) programs, a fixed wiring porosity, e.g. 50%, has been used for first and second level wiring through macro-circuit elements from which large-scale circuit arrays are laid out (grown). By adding key words to the EDS program for porosity control for both first and second level wiring to those describing the number of words and bits per word, more efficient use of semiconductor area is achieved. Limits to array or word dimensions caused previously by fixed porosity are also eliminated. Thus, what they are achieving is the creation of a plurality of units having a variety of different PF factors. In this manner, the units can be interchanged to meet global wiring concerns without adversely impacting function performance.